Most yield prediction work assumes that all the features in the
design are critical to the functioning of the chip. Hence, it is
not necessary to know details of particularly nodes, just the
results for all nodes. However some circuits are deliberately
designed with redundant nodes and repair strategies or there are
trade-offs that to be made between different faults (fatal and
``acceptable''). The yield analysis of such circuits requires a
detailed examination of the critical areas of nodes that can be
repaired and perhaps also the critical areas associated with the
repair circuitry. The peye-caa tool includes a number of feature to
help in the analysis of designs with redundancy or where design
trade-offs can be made.
Faults Between Selected Nodes
The simplest method is to separate out the nodes that are of
interest, to determine the critical area between named nodes or
groups of nodes. This could be useful for determining the
probability of a particular fault, one that is perhaps difficult to
test for or to estimate the impact of redundancy schemes.
The small script fragment,
$sel2=select_nodes($metal1,['sig16','sig15']);# select these nodes
$critval=FaultMapShorts($sel2,2,\@critlist);# Generate Critcal areas
push(@plotlist, @critlist);
push(@plotlist,($metal2,$metal1,$via1));
plotps("output.ps",\@plotlist); # plot the layer in the list
selects two metal1 signals (sig15 and sig16) and generates a
critical area measure of their interaction and a series (in this
case only 2 as they are widely separated) of critical area layers.
These critical area layers are plotted along with all the metal1,
metal2 and via1 layers. The output plot is shown below.
The selection of nodes shown above permits a limited analysis of
shorts between nodes. A full classification of extra material
critical area by node can also be obtained. The critical area for
individual faults is generated in a similar way to critical area,
except that every region which would result in separate unique node
interaction is identified and classified separately. There are a
number of operations within peye-caa to perform these extractions.
A "simple" high level operation FaultMapNodes will measure and
generate the critical area of any nodes that interact with some
defined nodes. A script fragment,
shows the generate of critical areas which relate to faults
involving any other node with one or both of nodes sig14 and sig15.
The output plot is shown below.
Example: Layout Optimization of an IC RAM Display.
An example where fault critical areas are useful is in IC based
display chips. In a display device single pixel drop out, while not
desirable, is acceptable, whereas column or global failure are
unacceptable. The layout of a liquid crystal static RAM integrated
circuit Spatial Light Modulator (SLM) pixel was analyzed for the
probability of pixel failure and global failure of shorting faults
on the metal 2 layer. Minor modifications were made to the layout
in order to minimise the unacceptable global faults at the expense
of ``acceptable'' pixel faults. These small adjustment to power
supply and control lines within the pixel enabled a 25% reduction
in the probability of global faults at the expense of an increase
in pixel faults of 10%. Column faults were not affected. The pixel
layout and the results before and after the minor layout
modification are shown below.
