The PEYE tool is a layout modification/analysis tool for the
automation of yield and reliability enhancement of IC layout and to
search out layout that is not optimal. The peye tool combines a
sophisticated polygon library with Perl (Practical Extraction and
Reporting Language). The tool permits complex layout modification
operations to be defined using the powerful language features of
Perl. PEYE has been used to add contacts/vias to designs and has
also been used as a wire spreader.
The peye tool has been interfaced with a sampling based yield
prediction system to enable the measurement of the layout
modifications and yield predictions based on these modifications.
This enables the very complex routines to be used to identify the
"amount" of a particular feature in a design, without having to
process the whole chip database. This makes the combined EYES and
PEYE package suitable for analysing large ICs in a reasonable
time.
PEYE can be used with the EYES sampling
system.
Results of a peye/eyes analysis to find "small transistors near
an inside corner(bend) in the active layer" are shown below. These
show the position (sampled measurement) all the transistors in the
design, and the areas where the target feature have been
identified.
