The PEYE-CAA tool provides the ability to generate and display
detailed critical areas of an IC design layout. It also has the
ability to find the critical
area between defined nodes , and so can be used to find the
probability of different faults. Typically it would be used by a
designer to review the layout of cells and small portions of
designs. Ideally this would be done interactively within a layout
editor. At present the tools can be interfaced to the, reasonably
priced, slam editor from Stabie-Soft (an
older interface to the Cadence layout editor is also available).
Alternatively a GDSII file of the cell or design can be used as
input, with output directed to a postscript file which can be
displayed or printed.
PEYE-CAA uses geometry manipulation to generate critical area
and is therefore suited for use in detailed design of library
cells. An example of an SRAM cell metal one layer and its critical
area map are shown below.
Maps and measurements of critical area can be used to highlight
area of a cell or design that can be improved. They can also
measure and so confirm the improvement once made.
If any chip or cell has been designed without taking the yield
of the layout into consideration, there will always be numerous
improvements that can be made. These improvement will give yield
and reliability gains. PEYE-CAA can make a real contribution to
identifying areas of layout that are not optimized for yield.
The PEYE software (Sun Solaris, Linux) is available for
evaluation without cost. To obtain an evaluate copy please fill out
an evaluation license agreement.
