Predictions Software

Press

EE Times, TSMC lifts lid on 45-nm design methodology

EE Times, TSMC DFM format empowers fabless design

EE Times, Partnering startups claim DFM sign-off tool

EE Times, SILICON PROCESSING: DFM software eyes random defects

EDA Confidential, EDA and Poker.

EE Times, Startup takes 'first step' toward integrating yield analysis into design.

EE Times, Scots startup brings yield prediction to designers.

Press Releases

26th April 2004, Standard and Custom Cell Yield and Critical Area Analysis via the Web.

9th January 2004 Design for Yield Interface to Slam IC Layout Editor.

Articles

EE Times 2004 What's yield got to do with IC design?

Targeted Layout Modifications for Semiconductor Yield/Reliability Enhancement, Semiconductor Manufacturing, IEEE Transactions on Publication Date: Nov. 2004 Volume: 17, Issue: 4 On page(s): 573- 581.