We develop products for yield prediction and yield enhancement of
IC layout. Our software tools and services are used by a number of
large IC manufacturers, who are members of SEMATECH.
Our world beating yield prediction tool EYES has been leased to fabrication plants in the
USA, Europe and Asia. The EYES tool uses the design layout and
fabrication defect data to make a very accurate yield prediction.
Predictions that are reliably better than +/- 1% have been reported
(ST, Crolles). The tool uses a patented sampling technique to make it possible to
quickly extract the critical areas of
state-of-the-art chips. Yield reports are generated in simple text,
html with chip maps and graphs, or in a spreadsheet format.
The PEYE-CAA tool is a version of
Perl that has been linked to the
eyes critical area library and additional display routines. This
makes it suitable for detailed critical area analysis(CAA) of parts
of a design or cell layout. This can be done interactively within a
layout editor or if your editor is not supported, simply using a
GDSII input and postscript output screen display. This capability
allows designers to see the areas of a chip layout that are most
sensitive to defects, and to measure the impact of their layout
modification efforts on reducing the critical area. The tool is
highly customizable.
PEYE -- Layout Analysis/Modifications to Enhance Yield
The PEYE tool is a version of Perl that has been linked to a
sophisticated polygon library. This makes it a very flexible tool
that can be used for simple operations, like generating and
displaying critical areas, or more complex operations, such as
analysing a layout for particalar features that might pose a DFM
issue. It has even been used to automatically adding extra vias to
an IC layout. The tool can be linked to the EYES tool to permit the
measurement of layout features by the sampling method. Since the modifications are
applied only to the samples, not the whole layout, detailed or
complex analysis can be undertaken to determine the amount of a
given feature and the regions of a chip where this feature is
found. This enables a much more detailed analysis to be routinely
performed than is usually practical.
