Critical area estimation (and hence yield prediction) by sampling
is based on the statistics of survey sampling [1]. Properties of a population can be
estimated, with bounds on the error of estimation, by taking a
number of random samples from the population. For example, the
estimate of the whole population mean, is given
by the sample average
,
= =
(1)
The estimated variance of
is,
() =
(2)
where N is the population size, n is the number of
samples and s2 is the sample variance,
s2 =
The bound on the error of estimation is,
2 = 2
(3)
An IC chip layout can be viewed as a population which has regions
with different susceptibilities to defects. By randomly sampling
the chip layout, an estimate of the critical areas for the whole
chip can be obtained. Survey sampling is particularly suited to IC
yield prediction since, for large populations, the error bound on
estimates does not depend on the population size but on the
variance of the population. This implies that the number of samples
required to characterise very large chips does not increase with
chip area or even its complexity but only with the variation of the
fault sensitivity over the chip. It is this property that enables
sampling to be used for even the largest layouts, as the variation
of layout fault sensitivity within a chip is not related to its
size.
Stratified Sampling
In many cases an improved method of estimating population
parameters can be obtain using stratified random
sampling [1]. A stratified
sample is generated by separating the population into a number of
non-overlapping regions, called strata. A simple random sample, as
described above, is then selected from each region. Stratified
sampling can increase the accuracy of population estimates where
the selected strata have less variance than the population as a
whole.
The estimator of the whole population mean, for a stratified survey is given by the stratified sample
average
,
= = Ni
(4)
the estimated variance of
:
() = Ni2()
(5)
where Ni is the population size of the ith
of L strata.
This technique can be usefully applied to the estimation of IC
critical areas by dividing up the layout area into a number of
regions (strata) for which the critical area is estimated using
either simple random sampling or systematic sampling [1]. Since IC layouts are usually composed
of large circuit blocks of similar layout types there is often less
variation locally than over the chip as a whole. Consequently a
stratified sampling scheme will nearly always result in a more
accurate estimate of total chip critical area with smaller bounds
on the error of estimation than an equivalent simple random
sample.
Sample Error Bounds
The average number of faults for each defect type can be estimated
by sampling the IC layout. Typically as many as 4000 samples would
be used to obtain an accurate measurement.
The chip yield is determined by combining a yield model with the
average number of faults per chip for each defect type. The bounds
on the error of the yield prediction can be calculated by
substituting the lower/upper error bounds of the average number of
faults into the yield model to determine the upper/lower error
bound on the yield. However, this may result in inaccurate error
bounds, since critical areas are normally correlated to some
degree.
More accurate estimates of error bounds can generated by making
use of a property of the Poisson model. This model allows a single
term
, the average number of
chip faults, to be derived from the sum of the average number of
faults for each defect type.
YTot
=
Y0e-
(6)
=
(7)
The sampled mean of
,
(where n
is the number of samples), is equal to the sum of the sample means
of ,
(where k is the
number of defect types), but the error bounds on
are not the
same and are typically smaller. This method has the effect of
reducing the variability of the sampled population, which is why
the error bounds improve. The sum of all the defect mechanisms
fault probabilities in a sample region is, in general, less
variable than that of a single defect mechanism. For example,
transistor gate area does not normally coincide with contacts. By
combining the fault mechanisms of transistor gate oxide pinholes
and contact failures the overall variability between sample regions
is reduced.
When the Poisson yield model is used to predict yield, the error
bounds of
can be used directly
to give the bounds of the predicted yield. For other models the
result are applied indirectly. Assuming the error bounds are small
a new yield model can be generated from the prediction,
YTot, of the existing model. The new model
(equation (9)), is based on the Poisson model
of equation (6), and gives the same yield
prediction using the term
and a constant
clustering factor Cf.
Cf
=
(8)
YTot
=
Y0e-Cf
(9)
This model is then used to give the error bounds on the original
prediction.