The ability to predict yield accurately is a useful end in itself
as it can be used for estimating cost of working chips and the
number of wafers required to achieve a given number of working
chips. However, perhaps the major benefit is in the area of yield
enhancement. The yield of a chip is a function of both the chip
layout and the process defects. It is possible to explore what
change in yield will result from changes in both the design layout and defect reductions in
the fab process.
Design layout changes are one
of the neglected areas of yield enhancement. Simple design layout
changes (process-design integration) offer a significant and
growing opportunity for overall yield enhancement.
In the fab, yield prediction helps by focusing on the true cost
of defects to the product. Better decisions can be made that target
effort in the most cost effective way to enhance the fab process yield.
