The yield of a chip design can be increased by either reducing the
defects in the fab process or changing the design so it is less
susceptible to those defects.
Traditionally yield improvement has been left to the people in
the fab. However, there are often major opportunities to change the
layout so that defects are less likely to cause faults.
The PEYE-CAA tool enables critical
area to be generated from GDSII or within a layout editor (
slam ). By
reducing the critical area, the yield is improved. The figure below
shows a simple example. The metal one layer of an SRAM cell has
been modified to reduce the probability of shorts between metal one
nodes. Click on the image for a larger version. The changes have
resulted in a greater than 10% reduction in the likely number of
faults.
Other areas of design enhancement use fault critical area to make best use
of redundancy strategies. For example, by making non-repairable
faults less likely, even at the expense of repairable faults. In
some circumstances it may be possible to make trade-offs between
acceptable and unacceptable faults, see an example
here.
The more advanced PEYE tool includes the
capabilities of PEYE-CAA but also
enables the design of automated layout modification from GDSII
design files. The tool is a very flexible layout manipulation
engine that combines the power of Perl with an advanced polygon
library. See the PEYE page for more
details.
